The use of copper as a conductive interconnect material is favored in semiconductor devices because of the high conductivities and circuit speeds copper enables. On the other hand, copper is difficult to pattern and copper interconnect leads have predominantly heretofore been formed using damascene and dual damascene processing technology whereby openings are formed in a dielectric layer on a substrate such as a semiconductor substrate used to form semiconductor devices. Copper is deposited over the dielectric layer and within the openings. Polishing/planarization removes copper from over the dielectric leaving the copper inlaid within the openings. In this way, the burden on photolithography is shifted from copper to the more manageable dielectric layer. The inlaid copper includes an upper surface that is essentially co-planar with the top surface of the patterned dielectric layer in which the copper is formed.
Subtractive copper etching is the alternative to a damascene process flow. A layer of copper is deposited and then patterned to form horizontal electrical interconnections. Early attempts to investigate subtractive copper etching used plasma excited halides which were found to provide many advantages but degraded the physical integrity of the copper near grain boundaries and other seams. There is renewed interest in subtractive copper etching since progress has been made in addressing these shortcomings. This renewed interest in subtractive copper etching brings renewed interest in associated properties of such a process. Thus, there is a need in the art to develop maintenance procedures unique to subtractive copper etching.